1. Field of the Invention
The present invention relates to the field of transistor techniques, and in particular to an organic thin film transistor (OTFT) and manufacturing method thereof.
2. The Related Arts
The organic thin film transistor (OTFT) is a type of TFT that uses organic substance as a semiconductor material, mostly used in plastic substrates due to the characteristics of curling and low manufacturing costs, and has become the most promising next-generation flexible display of the new array substrate technology. Compared with the traditional inorganic TFT, the OTFT manufacturing method is simpler and has lower requirements on the conditions and the purity of the film forming atmosphere, so the manufacturing cost is lower. The OTFT shows excellent flexibility and is suitable for flexible display, electronic skin, flexible sensors, and so on.
The materials for the OTFT organic semiconductor (OSC) layer are mainly polymer and small molecule, and the organic insulating (OGI) layer used with the OSC layer usually uses organic materials, such as, poly 4-ethylphenol (PVP), poly vinyl alcohol (PVA), or cytop. The interface between the OSC layer and the OGI layer has a defect state. When the OTFT is subjected to the stress due to a gate voltage for a long time, the charges are often trapped at the interface, causing the device threshold voltage (Vth) to drift (shift), leading to deterioration of device performance.
FIG. 1 shows a schematic view of a conventional OTFT structure. The conventional OTFT mainly comprises a substrate 10, a source/drain electrode layer 11 formed on the substrate 10, an organic semiconductor layer 12 formed on the source/drain electrode layer 11, an organic insulating layer 13 formed on the organic semiconductor layer 12, and a gate electrode layer 14 formed on the organic insulating layer 13; the remaining layers may further comprises an organic planarization layer (not shown) formed on the gate electrode layer 14, and so on. The description is omitted here.
When the TFT stays on for a long time, the gate electrode of the gate electrode layer 14 will be in a state of negative bias voltage (such as, Vgs=−40V) for a long time. At this time, the hole trapping will occur at the interface between the organic semiconductor layer 12 and the organic insulating layer 13, making the device difficult to turn on, causing Vth to shift to the left.
FIG. 2 is a schematic diagram of Vth left drift of a conventional OTFT, and is an example of a Vth left drift of a TFT under negative bias thermal stress (NBTS). In FIG. 2, the horizontal axis represents the gate voltage Vg in volts and the vertical axis represents the drain current Id in amps. The corresponding time of the Vth curve increases from 0 second to 2000 seconds, and the Vth curve drifts to the left.